Power Optimization of Glitch Free NAND Based Digitally Controlled Delay Lines

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Provided by: International Journal of Communication and Computer Technologies (IJCCTS)
Topic: Hardware
Format: PDF
The recently proposed NAND-based Digitally Controlled Delay-Lines (DCDL) present a glitching problem which may limit their employ in many applications. This paper presents a glitch-free NAND-based DCDL which overcame this limitation by opening the employ of NAND-based DCDLs in a wide range of applications. The proposed NAND-based DCDL maintains the same resolution and minimum delay of previously proposed NAND-based DCDL. The theoretical demonstration of the glitch-free operation of proposed DCDL is also derived in the paper. Following this analysis, three driving circuits for the delay control-bits are also proposed.
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