Power Optimized Divide-by-2/3 Counter Based Clock Design using Multiplexer
In this paper, the authors propose advanced method of Extended True-Single-Phase-Clock (E-TSPC) based divide by- 2/3 counter design for providing low supply voltage and low power consumption. The counting logic and the mode selection control can be designed by the help of single transistor using wired OR method. The proposed method mainly focus on for saving power consumption and it reduces the critical path between the E-TSPC Flip Flops (FFs) for improving the operating frequency of the counter. E-TSPC will reduce the design time, Layout area, in power-delay-product and increase the operation speed can be achieved by the proposed design and expected 1.0 to 2.0% of power reduction.