Power Reduction for Sequential Circuit Using Merge Flip-Flop Technique

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Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Topic: Hardware
Format: PDF
Flip-flops are the major storage element and most power consumption component in a sequential circuit. In integrated circuits, the power consumed by clocking is more than 50% of the system power because of its transition probability. Given a design, the authors can reduce its power consumption by replacing several flip-flops with some multi-bit flip-flop. This may affect the performance of the original circuit because of its timing and placement capacity constraints. To overcome this problem efficiently, a technique combination table is introduced to enumerate possible combinations of flip-flops provided by a library.
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