Power Reduction in CMOS Sub-Threshold Dual Mode Logic Circuits by Power Gating

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Provided by: Iosrjournals
Topic: Hardware
Format: PDF
Power dissipation has always been a major concern in integrated circuit design. Even during static state, there is a small amount of leakage power. In this paper, the authors have implemented various power gating techniques like sleep, dual sleep and sleepy stack in sub-threshold dual mode logic circuits. This logic can bring down the total power. Hence, a comparative analysis of power consumption is performed. The dual mode logic has two modes of operation namely static and dynamic.
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