Power Scaling in CMOS Circuits by Dual-Threshold Voltage Technique

Provided by: International Journal of Engineering and Innovative Technology (IJEIT)
Topic: Hardware
Format: PDF
Reducing power dissipation has become an important objective in the design of digital circuits. One common technique for reducing power is to reduce the supply voltage. For CMOS circuits the cost of lower supply voltage is lower performance. Scaling the threshold voltage can limit this performance loss somewhat but results in increased static power dissipation. In modern digital integrated circuits, power consumption can be attributed to three main components: short circuit, leakage and dynamic switching power in fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5V.

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