Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. The authors investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns.

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