Institute of Electrical & Electronic Engineers
System-on-Chip (SoC) design is experiencing a radical shift from uniprocessor architecture to multi-processor architecture in order to adjust with the ever increasing demand for high performance. Design-time strategies are suited only for mapping predefined set of applications and thus cannot predict dynamic behavior. This dynamism demands run-time mapping of application tasks to maintain a critical balance between performance and resource optimization. This paper proposes a run-time heuristic that intelligently distributes the application tasks among multiple processors taking communication overhead, computation load and resource utilization in consideration.