International Journal of Electronics Communication and Computer Engineering
Due to the challenge that the number of cores is combined on a single chip, the Network-on-Chip (NoC) has gradually become a popular solution. And recently, researchers have focused on improving the performance of NoC chips to achieve good performance. In this paper, the authors present an algorithm configuration for network-on-chip architecture with reconfiguration ability for designing NoC with specific use. NoC architecture with reconfigurable capability reduces the complexity of the design and makes the layout of the NoC relatively more flexible compared to the layout of creating the topology map and the mapping design.