University of Teramo
Reduced or bounded power consumption has become a first-order requirement for modern hardware design. As a design progresses and more detailed information becomes available, more accurate power estimations become possible but at the cost of significantly slower simulation speeds. Power simulation that is both sufficiently-accurate and fast would have a positive impact on architecture and design. In this paper, the authors propose PrEsto, a power modeling methodology that improves the speed and accuracy of power estimation through FPGA-acceleration.