Prioritized Direction Based Switch for Bufferless Network on Chip Architecture
This paper represents a bufferless Network on Chip (NoC) architecture for a generic multi-array based architecture. A weighted priority based routing technique will be employed that handles contention based on destination direction. The results will represent the comparative effectiveness of the design with a XY based switch. Matrix multiplication application is tested and mapped as the Process Entities (PEs) to demonstrate the effectiveness of the NoC design. The NoC architecture is synthesized and tested on FPGA platform as a prototype.