Procedure Hopping: A Low Overhead Solution to Mitigate Variability in Shared-L1 Processor Clusters

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Variation in performance and power across manufactured parts and their operating conditions is a well-known issue in advanced CMOS processes. This paper proposes a resilient HW/SW architecture for shared-L1 processor clusters to combat both static and dynamic variations. The authors first introduce the notion of Procedure-Level Vulnerability (PLV) to expose fast dynamic voltage variation and its effects to the software stack for use in runtime compensation. To assess PLV, they quantify the effect of full operating conditions on the dynamic voltage variation of a post-layout processor in 45nm TSMC technology. Based on their analysis, PLV shows a range of 18mV

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