Process Variation Aware Data Management for STT-RAM Cache Design

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Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
The Spin-Transfer Torque Random Access Memory (STT-RAM) has gained increasing attentions for its high density, fast read access, zero standby power, and good scalability. The recently proposed retention-relax design further improves STT-RAM write access performance and makes it even more promising as an on-chip memory technology. Nevertheless, the process variations could affect the writability of STT-RAM cells. The situation for retention-relax design is even more severe. In this paper, the authors comprehensively study the impact of process variations, including those from both CMOS and magnetic technologies, on key STT-RAM design parameters.
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