Processor Caches Built Using Multi-Level Spin-Transfer Torque RAM Cells

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Provided by: University of Pitesti
Topic: Storage
Format: PDF
It has been predicted that a processor's caches could occupy as much as 90% of chip area for technology nodes from the current. In this paper, the authors study the use of multi-level Spin-Transfer Torque RAM (STT-RAM) cells in the design of processor caches. Compared to the traditional SRAM caches, a Multi-Level Cell (MLC) STT-RAM cache design is denser, fast, and consumes less energy. However, a number of critical issues remains to be solved before MLC STT-RAM technology can be deployed in processor caches. In this paper, they shall offer solutions to the issue of bit encoding as well as tackle the write endurance problem. The latter has been neglected in previous works on STT-RAM caches.
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