International Journal of Engineering Trends and Technology
In this paper, the authors present the eight bit CMOS base incrementer and decrementer logic design using eight bit adder and subtractor. The parametric simulation is done on MICROWIND layout editor tool. The any conventional static CMOS adder with pull-up and pulldown logic requires 32 MOSFET whereas their design adder requires 30 MOSFETs. Their design methodology is based on static CMOS logic and transmission gate logic to achieve smaller delays, reduce power dissipation and optimized area.