Propagation Delay Based Comparison of Parallel Adders
An intelligent full adder circuit is simulated using Cadence Virtuoso analog design version 6.0. The complementary property between sum and carry for most of the input combination is considered for reducing the number of transistors in the full adder circuit. The parameters such as the power consumption, delay and Power Delay Product (PDP) are improved in the proposed CMOS full adder than the conventional CMOS full adder. The size of the chip and the number of transistors are greatly reduced with the proposed circuit.