Provided by: Hikari
Date Added: Nov 2013
The reduction of pattern area and delay time for logic circuit using newly proposed DTMOS type SGT with the same power consumption compared to that using conventional SGT are described. The reduction of delay time of logic circuit such as inverter and NAND circuit with small channel width using DTMOS type SGT is presented. The delay times of these circuits with DTMOS type SGT can be reduced to 64%-77% compared to that with conventional SGT with supply voltage of 0.5V.