International Journal of Computer Science and Network Security
Application of Multiple-Valued Logic (MVL) in the design of digital devices opens additional opportunities. D flip-flop is a basic sequential circuit in any logic. A 4-bit counter using multiple-valued D flip-flops is presented in this paper. D flip-flop is built by 3 input NMIN gates and has both preset and clear inputs. Quaternary multiplexer and D flip-flops are used to design the quaternary counter. The circuits being studied are optimized for power and delay at 0.18-um CMOS process technology. The new D flip-flop designed here shows 64.33% improvement in dynamic power dissipation when compared to DLC based flip-flop and Q-IDEN D flip-flop.