Randomized Partially-Minimal Routing Architecture for 3-D Mesh Network on Chips

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Provided by: International Journal of Engineering Research and Development (IJERD)
Topic: Hardware
Format: PDF
Programmable many-core processors are poised to become a major design option for many embedded applications. In the design of power-efficient embedded many-core processors, the architecture of the on-chip network plays a central role. Many designs have relied on 2D mesh architecture as the underlying communication fabric. With the emergence of 3D technology, new on-chip network architectures are possible. The increasing viability of 3-D silicon integration technology has opened new opportunities for chip architecture innovations. One direction is in the extension of 2D mesh-based tiled chip multiprocessor architectures into three dimensions.
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