Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D2-CMP) using FPGAs
In this paper, the authors present the FPGA implementation of the prototype for the Data-Driven Chip Multi-Processor (D2-CMP). In particular, they study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator.
Subscribe to the Innovation Insider Newsletter
Catch up on the latest tech innovations that are changing the world, including IoT, 5G, the latest about phones, security, smart cities, AI, robotics, and more. Delivered Tuesdays and Fridays