Realization of Static Write Margin of Hybrid Set-CMOS Based 6-T SRAM Cell
In this paper, the authors' present research endeavor focuses on the factors of hybrid Single Electron Transistor (SET)-CMOS based Static Random Access Memory (SRAM). Ultra small low power dissipated SET is combined with high gain and high current drivable CMOS and the write operation of the memory cell is briefly analyzed. This paper is a comparative work of power consumption between conventional CMOS based SRAM and hybrid SET-CMOS based SRAM. All the simulations have been done with the help of MIB and BSIM4.6.1 models in tanner environment to realize the robustness and novelty of their presented model.