In this paper, the authors propose a parity generator and checker designed using reversible logic with a CMOS header switching for power gating. Reversible logic uses logic gates with zero heat dissipation. The main functional building blocks of computational units are the adder blocks. The computation process produces results based on the incoming inputs. If incoming inputs are same then the computation need not be done again, as the results are already computed and available for the same. So a large amount of power and memory can be saved. This is achieved by the CMOS header switching mechanism. The proposed circuit is based on time constraint and have been simulated for better power saving and memory usage.