University of Calgary
CMP is a planarization technique for multilevel VLSI metallization processes. CMP fills are inserted as a Design For Manufacturability (DFM) methodology to improve pattern-dependent post-CMP topography, i.e., to improve interconnect planarity. Design-driven fill synthesis seeks to optimize CMP fill with respect to objectives beyond mere density uniformity. Design-driven fill synthesis minimizes the impact of CMP fill on function-driven performance and parametric yield metrics, while satisfying manufacturing-driven density criteria. This paper reviews CMP fill techniques as a DFM process, then describes a power-aware methodology wherein CMP fill synthesis is integrated within a holistic design- and manufacturing-driven flow.