Reconfigurable Architecture for Network processing

The proposed GF(2193) is based on an efficient Montgomery add and double algorithm, also the karatsuba-offman multiplier and Itoh-Tsjuii algorithm are used as the inverse component. The hardware design is based on optimized Finite State Machine (FSM), with a single cycle 193 bits multiplier, field adder and field squarer. The different optimization at the hardware level improves the acceleration of the ECC scalar multiplication; increases frequency and the speed of operation such as key generation, encryption and decryption. Finally the authors have to implement their design using Xilinx XC4VLX200 FPGA device.

Resource Details

Provided by:
International Journal of Computer Applications
Topic:
Hardware
Format:
PDF