Reconfigurable CPL Adiabatic Gated Logic -RCPLAG Based Universal NAND/NOR Gate

Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
In precursory efforts, authors have illustriously consolidated the benefits of CPL based circuits and adiabatic logic conjoint the use of clock for even combinational blocks and reported the power diminution. With the adhibition of clock in combinational blocks, the same circuit topology may be employed for sequential behavior as manifested by authors in their erstwhile works. Proceeding forward in the same direction and augmenting another edge into this, authors have reported the reconfigurable circuit implementation utilizing the reported CPLAG concepts.

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