Reconfigurable Efficient Design of BCH Encoder for Communication Systems

In this paper, the authors propose a design and FPGA implementation of SISO BCH encoder. FPGA's are reprogrammable and they require shorter testing and debugging times, thus making them increasingly popular for rapid hardware prototyping. Reconfigurable systems also offer the potential of accelerating or speeding up the algorithms to be implemented by exploiting the parallelism. It has been found that among all the codes BCH codes are most efficient because they have the capability to correct multiple errors that occur at any instant.

Provided by: International forum of researchers Students and Academician Topic: Networking Date Added: Nov 2014 Format: PDF

Find By Topic