REDEFIS - A System with a Redefinable Instruction Set Processor

Download Now
Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
The growing complexity and production cost of processor-based systems have imposed big constraints in System-on-Chip (SoC) design of new systems. GPPs and ASICs are unable to fit the tight performance or power constraints, or too complex to design in short TAT/TTM. REDEFIS is a HW/SW design platform for high level, efficient implementation of ASIPs/engines for System-on-Chip (SoC) systems. It is composed of a reconfigurable instruction-set processor, capable to redefine its ISA according to the user application written in high level C language, and a set of design tools (an ISA Generator and a retargetable compiler).
Download Now

Find By Topic