Reduce, Reuse, Recycle (R3): a Design Methodology for Sparse Matrix Vector Multiplication on Reconfigurable Platforms

Provided by: Iowa State University
Topic: Hardware
Format: PDF
Sparse Matrix Vector multiplication (SpMV) is an important computational kernel in many scientific computing applications. Pipelining multiply-accumulate operations shifts SpMV from a computationally bounded kernel to an I/O bounded kernel. In this paper, the authors propose design methodology and hardware architecture for SpMV that seeks to utilize system memory bandwidth as efficiently as possible, by reducing the matrix element storage with on-chip decompression hardware, reusing the vector data by mixing row and column matrix traversal, and recycling data with matrix-dependent on-chip storage.

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