Reduced Area Carry Select Adder with Low Power Consumptions

Provided by: Creative Commons
Topic: Hardware
Format: PDF
In many computers and other kinds of processors the adder is the most commonly used arithmetic block. In this paper, the authors proposed an area-efficient carry select adder that also having low power consumptions. In this, by sharing the common Boolean logic term, they can reduce the duplicated adder cells that used in the conventional carry select adder. So they only need one XOR gate and one inverter gate for each summation operation as well as one AND gate and one OR gate in each carry-out operation.

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