International Journal of Computer Applications
In this paper, the authors discuss Hybrid Ripple Carry Look-ahead Adder (HRCLA), which is a hybrid between Carry Look-ahead Adder (CLA) and Ripple Adder (RA). In HRCLA time is traded off for area and power. HRCLA has been designed by rippling the last carry bit of a 4-bit CLA. HRCLA extracts the traits of Carry Look-ahead Adders (CLA) speed and Ripple Adders (RA), area. A four bit proposed HRCLA has been implemented in Cadence using 45nm technology; the implementation results showed 12.2% Area, 4.6% power improvement and 14.01% critical path delay overhead over CLA.