Science & Engineering Research Support soCiety (SERSC)
In this paper, the authors presents a VLSI (Very Large Scale Integrated) implementation of reduced -complexity and reconfigurable MIMO (Multiple-Input Multiple-Output) signal detector targeting 3GPP-LTE (3rd Generation Partnership Project-Long Term Evolution) standard. In recent wireless communication system, MIMO technology is considered as the key technique in LTE to meet the target. Maximum Likelihood (ML) detection is the optimal detection algorithm for MIMO systems. FPGA (Field Programmable Gate Array) implementation of ML detector becomes infeasible as its complexity grows exponentially with the increase in number of antennas.