Advances in semiconductor process technology have enabled processors and System On Chip (SOC) to have an excess of billion transistor count. Leakage power becomes big percentage of total active power especially for small geometry CMOS technology. It is estimated that 20-50% of total average power during normal operation lost to leakage power. Leakage power is even more important for mobile devices where ideal time is long and battery life is important. This paper presents a low leakage SRAM cell and array architecture targeting high performance, low power embedded memory.