Reducing Cache and TLB Power by Exploiting Memory Region and Privilege Level Semantics

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Provided by: Reed Business Information
Topic: Hardware
Format: PDF
In the past decade, the general-purpose microprocessor industry has gone through a shift from performance-first to energy-efficient computing. Computer architects invented and investigated methods to optimize power consumption of literally every component of the processor. In contrast with most other units of the chip, the first-level cache in commercial general-purpose processors has seen rather limited application of micro-architectural power efficiency optimizations. The L1 cache in today's high-performance processors accesses all ways of a selected set in parallel. This constitutes a major source of energy inefficiency: at most one of the N fetched blocks can be useful in an N-way set-associative cache.
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