International Journal of Engineering Sciences & Research Technology (IJESRT)
Depends on various requirements the paper presents & optimized Rivest-Shamir-Adleman (RSA) processor which satisfies circuit area, operating time. The authors also introduce 3 multiplier based data path using different intermediate data forms: single form, semicarry-save form and carry-save form, and combined them with a wide variety of arithmetic components. A total of 242 data-paths for 1024-bitRSA processors were obtained for each radix. They can reduce the RSA runtime up to 0.24ms. As a result, the fastest design can perform the RSA operation in less than 1.0ms.