Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems

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Provided by: University of Calgary
Topic: Data Centers
Format: PDF
In this paper the authors describe an architecture and FPGA synthesis tool-chain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is amenable to automatic, semi-automatic, or even manual parallelization. Whereas accelerator approaches have traditionally achieved energy benefits as a side effect from increasing performance via parallel execution, ICERs aim to achieve energy gains even on code with little exploitable parallelism.
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