Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, FPGA architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primarily adders and subtractors). Inspired by the carry chains, the authors generalize the idea to connect Look-Up Tables (LUTs) in adjacent logic cells.
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