Reduction of Bitstream Transfer Time in FPGA

Provided by: Iosrjournals Topic: Hardware Date Added: Apr 2014 Format: PDF
Field programmable gate array are revolutionary device which combine the benefits of hardware and software. In reconfigurable system, the size of bitstream and memory is reduced using bitstream compression. By reducing the reconfiguration time, the system can improve the communication bandwidth. Existing system shows that, at the cost of compression efficiency effective compression is achieved with slow or fast decompression rate. To improve both compression and decompression efficiencies, this paper proposes a new technique i.e., decode aware compression technique.

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