Reduction of Delay and Power by Using MLDD Technique in Error Correction

In this paper, the authors present an error-detection method for Euclidean Geometry Low Density Parity Check (EG-LDPC) codes with majority logic decoding methodology. The algorithm is synthesized in Xilinx 12.1 and simulated using Modelsim 5.7g. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces the delay time by detecting the errors in parallel and in pipelining manner.

Provided by: The International Journal of Innovative Research in Computer and Communication Engineering Topic: Storage Date Added: Mar 2014 Format: PDF

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