Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies

As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip's power draw. This is unfortunate, given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data. An effective way to reduce this problem is to use a low-leakage technology such as embedded DRAM (eDRAM). However, eDRAM requires refresh. In this paper, the authors examine the opportunity of minimizing on-chip memory power further by intelligently refreshing on-chip eDRAM.

Provided by: University of Illinois at Urbana Champaign Topic: Storage Date Added: Jan 2013 Format: PDF

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