Relaxed Memory Models Must Be Rigorous

Provided by: INRIA
Topic: Hardware
Format: PDF
Multiprocessors and high-level languages generally provide only relaxed (non-sequentially-consistent) memory models, to permit performance optimizations. One has to understand these models to program reliable concurrent systems - but they are typically ambiguous and incomplete informal-prose documents, sometimes give guarantees that are too weak to be useful, and are sometimes simply unsound. Based on the authors' previous paper, they review various problems with some current specifications, for x86 (Intel 64/IA32 and AMD64), and power and ARM processors, and for the java and C++ languages.

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