Institute of Electrical & Electronic Engineers
In sub-65nm CMOS process technologies, Network-on-Chip (NoC) is increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints. In this paper, the authors propose a novel design-time framework to trade-off energy consumption and reliability in the NoC fabric at the system level for MPSoCs.