Reliability Aware Negative Bit-Line Voltage Write Assist Scheme for SRAM
In nanoscale CMOS technologies, SRAMs employ aggressively small cells, which make them extremely vulnerable to process variations, degrading the write-ability of SRAM. The increased effect of process variations in nanoscale technologies requires additional techniques and treatments such as write assist techniques to ensure fast and reliable write operation. Many write assist techniques e.g. reduce VDD at cell, raise VSS at cell, WL (Word-Line) boost, strengthen pass gate NMOS, weaken pull-up PMOS, negative bit-line scheme have been presented earlier, out of which negative bit line voltage scheme and WL (Word-Line) boost scheme have been found two most promising solutions for assisting write operation of SRAM.