Reliable Code Generation and Execution on Unreliable Hardware Under Joint Functional and Timing Reliability Considerations

To enable reliable embedded systems, it is imperative to leverage the compiler and system software for joint optimization of functional correctness, i.e., vulnerability indexes, and timing correctness, i.e., the deadline misses. In this paper, the authors consider the optimization of the Reliability-Timing (RT) penalty, defined as a linear combination of the vulnerability indexes (reliability penalties) and the deadline misses. The authors propose a multi-layer approach to achieve reliable code generation and execution at compilation and system software layers for embedded systems.

Provided by: Institute of Electrical & Electronic Engineers Topic: Hardware Date Added: Jun 2013 Format: PDF

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