Provided by: edaa
Date Added: Jan 2011
The reliability of Networks-on-Chip (NoC) is threatened by low yield and device wearout in aggressively scaled technology nodes. The authors propose ReliNoC, a network-on-chip architecture which can withstand failures, while maintaining not only basic connectivity, but also quality-of-service support based on packet priorities. Their network leverages a dual physical channel switch architecture which removes the control overhead of Virtual Channels (VCs) and utilizes the inherent redundancy within the 2-channel switch to provide spares for faulty elements. Experimental results show that ReliNoC provides 1.5 to 3 times better network physical connectivity in presence of several faults, and reduces the latency of both high and low priority traffic by 30 to 50%, compared to a traditional VC architecture.