Research on Reliable Network-on-Chip Architecture Using Asynchronous Logic

Provided by: AICIT
Topic: Hardware
Format: PDF
The development of silicon technology follows Moore's law and integrated circuits enter deep submicron era. New technology makes System-On-Chip (SoC) design more difficult: on one hand, logic and wire delays become unpredictable; on the other hand, SoC integrate a large number Intelligence Properties. The exponential development of Integrated Circuits (IC) brings huge challenge to traditional System-on-Chip (SoC) interconnects. The paper focuses on reliable on-chip interconnect and proposes a delay insensitive asynchronous on-chip network to provide high-performance, high-reliable and extensible on-chip interconnection.

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