Resilience Articulation Point (RAP): Cross-Layer Dependability Modeling for Nanometer System-on-Chip Resilience

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Provided by: Reed Business Information
Topic: Hardware
Format: PDF
The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System-on-Chip (SoC). RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flips. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables.
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