Resistive Computation: Avoiding the Power Wall With Low-Leakage, STT-MRAM Based Computing

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in sub-threshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multi-core processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multi-core scaling will soon hit a power wall.

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