Institute of Research and Journals (IRAJ)
Functional verification is one of the major challenges in chip design today, with test generation, test bench construction and simulation consuming a significant portion of the design effort. Verification is a process used to demonstrate the functional correctness of a design. Also called logic verification or simulation. This paper demonstrates the functional verification planning process for creating reusing and reconfigurable verification systems (test bench) which can be used to verify different versions of a component design with minimum changes in the verification environment by using minimum components for creating verification environment.