Reuse-Aware Modulo Scheduling for Stream Processors

Provided by: edaa
Topic: Hardware
Format: PDF
In this paper, the authors present reuse-aware modulo scheduling to maximizing stream reuse and improving concurrency for stream-level loops running on stream processors. The novelty lies in the development of a new representation for an unrolled and software-pipelined stream-level loop using a set of reuse equations, resulting in simultaneous optimization of two performance objectives for the loop, reuse and concurrency, in a unified framework. They have implemented this paper in the compiler developed for their 64-bit FT64 stream processor.

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