Journal of Theoretical and Applied Information Technology
Designing high-speed multipliers with low power and regular in layout have substantial research interest. The analysis is done on the basis of certain performance parameters i.e. area, speed and power consumption and dissipation. Multipliers are considered to be an important component in DSP applications like filters. Therefore, the low power multiplier is a necessity for the design and implementation of efficient power-aware devices. In this paper, the authors have analyzed and reviewed a few multiplier architectures based on their working principle, speed and power efficiency.