Review of Hardware Task Placement Algorithms for Partially Reconfigurable FPGAs
In this paper, the authors deal with the study of major addressing problem in the operating system of reconfigurable computing platform. Demand of high performance and more flexibility of various dynamic applications such as embedded systems, signal and image processing etc., can be satisfied by the reconfigurable Field Programmable Gate Arrays (FPGAs). The incoming tasks can be placed and removed dynamically in the FPGAs and also it allows one or more tasks to compute at a time (i.e., truly multitasking). The performance of this device completely depends on how the limited resources of FPGA shared among the incoming tasks.